Time-Domain Equalizer

ABSTRACT

The present invention provides a cost-effective TEQ hardware architecture to support multiple VDSL2 profiles. It supports variable TEQ tap length programmable through firmware. Larger TEQ tap length at low-speed profiles is supported by the unique design without adding additional multipliers. The maximum number of TEQ taps supported is actually inversely proportional to the profile frequency. This perfectly meets the requirement to have longer TEQ for low-speed profile and shorter TEQ for high-speed profile.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims the benefit of provisional applicationNo. 60/755,365 filed Dec. 29, 2005, the content of which is herebyincorporated by reference in its entirety.

FIELD OF THE INVENTION

The present invention relates to a time-domain equalizer, moreparticularly to a novel time-domain equalizer hardware architecture forsupporting multiple VDSL2 profiles.

BACKGROUND OF THE INVENTION

VDSL2 refers to second-generation very-high speed digital subscriberline and the first draft standard (G.993.2) was proposed in May 2005 bythe International Telecommunication Union (ITU). VDSL2 is an evolvingDSL technology that aiming at delivering high data rate through copperpairs. The supported data rate can be up to 100 Mbps at each directionof downstream and upstream. Different profiles are created in order tomeet the requirement of different deployment scenarios mostly related tothe loop distance. The following table shows all the supported profiles:

VDSL2 profiles Parameter value for profile Frequency plan Parameter 8a8b 8c 8d 12a 12b 17a 30a All Maximum +17.5 +20.5 +11.5 +14.5 +14.5 +14.5+14.5 +14.5 aggregate downstream transmit power (dBm) All Maximum +14.5+14.5 +14.5 +14.5 +14.5 +14.5 +14.5 +14.5 aggregate upstream transmitpower (dBm) All Sub-carrier 4.3125 4.3125 4.3125 4.3125 4.3125 4.31254.3125 8.625 spacing(s) (kHz) All Support of Required Required RequiredRequired Required Not Not Not upstream Required Required Required bandzero (US0) All Minimum net 50 Mbit/s 50 Mbit/s 50 Mbit/s 50 Mbit/s 68Mbit/s 68 Mbit/s 100 Mbit/s 200 Mbit/s aggregate data rate capability(Mbit/s) All Aggregate 65,536 65,536 65,536 65,536 65,536 65,536 98,304131,072 interleaver and de-interleaver delay (octets) All D_(max) 20482048 2048 2048 2048 2048 3072 4096 All 1/S_(max) 24 24 24 24 24 24 48 28downstream All 1/S_(max) 12 12 12 12 24 24 24 28 upstream

Lower profiles such as 8a˜12b are used to support medium range looplength with a distance between 3 kft to 8 kft while high speed profiles17a˜3a are used to support short range loop length of less than 3 kft.Only 30 MHz profile 30a is able to support 100 Mbps on both upstream anddownstream while 17 MHz profile 17a can support aggregated 100 Mbps.

Time-domain equalizer is a technology aiming at shortening the channelresponse length so that the inter-symbol-interference betweenconsecutive DMT frames can be alleviated. The time-domain equalizer isusually implemented as a FIR filter. The number of FIR taps depends onthe loop length. Usually longer loop requires longer FIR filter. On theother hand, longer loop means lower transmission band since strongattenuation on the high frequency makes SNR low and effectively no bitcan be loaded. Therefore, longer loop also implies low profiles such as8.5 MHz etc.

The VDSL2 standard defines multiple profiles to support differentfrequency ranges from 8.5 MHz to 30 MHz. The backward compatibilityrequirement further extends the VDSL2 frequency as low as 1.104 MHz.Time-domain equalizer is usually used to reduce theinter-symbol-interference across neighboring symbols. To achieve anoptimal system performance, the required number of TEQ taps is differentfor different profiles. High-speed profiles such as 17 MHz and 30 MHzrequire less TEQ taps due to short loop distance. Low-speed profilessuch as ADSL2 spectrum 2.208 MHz or 8.5 MHz require higher number of TEQtaps due to longer channel response caused by the long loop distance.Therefore, it is very important to design cost-effective time-domainequalizer hardware to meet different profile requirement if amulti-profile ASIC solution is desired.

SUMMARY OF THE INVENTION

One of most costly hardware components in the time-domain equalizer ismultiplier. In order to reduce the hardware cost of the time-domainequalizer as well as to reduce the power consumption, a careful designis needed to optimize the use of multipliers. In this proposal, wepropose a unique TEQ hardware architecture based on this objective. OurTEQ architecture can be programmable to support longer TEQ filter lengthwith the same number of multipliers when low-frequency profiles such as8.5 MHz or ADSL2 spectrum are used.

The present invention provides a cost-effective TEQ hardwarearchitecture to support multiple VDSL2 profiles. It supports variableTEQ tap length programmable through firmware. Larger TEQ tap length atlow-speed profiles is supported by the unique design without addingadditional multipliers. The maximum number of TEQ taps supported isactually inversely proportional to the profile frequency. This perfectlymeets the requirement to have longer TEQ for low-speed profile andshorter TEQ for high-speed profile.

In accordance with the present invention, a time-domain equalizercomprising M_(OPT) multipliers,

$M_{OPT} = \left\lfloor {\max \left( {\frac{T_{0}}{N},\frac{T_{1}}{2N},\frac{T_{2}}{4N},\frac{T_{3}}{16N}} \right)} \right\rfloor$

wherein T₀ being the taps required by the 30a profile of VDSL2, T₁ beingthe taps required by the 12a, 12b, 17a profile of VDSL2, T₂ being thetaps required by the 8a, 8b, 8c, 8d profile of VDSL2, T₃ being the tapsrequired by ADSL2+ downstream; and the factor N≧1 and usually beingchosen as an integer; and wherein the multiplier carrying out amultiplication operation at every system clock cycle.

In accordance with one embodiment of the invention, the said equalizeris configured so that the ADC_DATA coming from the ADC in theanalog-front-end is pushed into the time-domain equalizer depending onthe Nyquist frequency of the profile; the ADC_DATA_RDY is used toqualify the ADC_DATA and the ADC_DATA_RDY assertion will advance thedata delay-line (MUXs) among the delay line registers (d( . . . )Regs);the Stage l Counter to control which taps and corresponding coefficientsare multiplexed into the M_(OPT) multipliers, it being reset by theADC_DATA_RDY assertion and then it will start the counting process fromzero until it reaches the configuration register L; the results of thosemultiplications are summed together; the accumulator basicallyaccumulates and stores the summation results for different stages; whenthe Stage l Counter is reset to zero and the first summation

$\sum\limits_{k = 0}^{M_{OPT}}{{d(k)}{c(k)}}$

is directly clocked into the accumulator; otherwise, the accumulator isadded together with the summation from the current stage and stored; andwhen the Stage l Counter reaches the final stage L, it will signal theTEQ_OUT_RDY to next module in the data-path to latch the TEQ_OUT_DATAfrom the accumulator.

In accordance with another embodiment of the invention, the saidequalizer further comprising to utilize the time-shared multipliers tosupport different time-equalization requirement for different profilesso that it can support longer deployment loops without additionalmultipliers for finite impulse response filter.

Our focus is VDSL2 application. However, the same technology isapplicable to other applications such as WiMAX etc.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features, aspects, and advantages of the presentinvention will become better understood with regard to the followingdescription, appended claims, and accompanying drawings, where:

FIG. 1 shows the time-domain equalizer hardware architecture formultiple VDSL2 profile support in accordance with the present invention.

DETAILED DESCRIPTION OF THE MENTION Time-Domain Equalizer Architecture

To understand our TEQ architecture, it is necessary to understand therelationship between our system clock frequency and the profile-specificfrequency. Each profile actually defines a minimum frequency requirementthat used at the physical layer, which is basically the Nyquistfrequency or twice of the profile frequency. The sampling frequency onthe AFE can be different depending on if or no over-sampling is used. Onthe other hand, the system clock frequency is basically the clockfrequency used to drive the digital data-path circuit such as ourtime-domain equalizer. In general, the choice of the system clockfrequency should be based on the highest physical frequency as well asthe computational requirement across all the data-path modules. In thecase of VDSL2, the highest physical frequency comes from the 30 MHzprofile, which has 4096 sub-carriers and 8.625 KHz tone spacing. Thismeans that the sampling frequency for the analog-to-digital converterneeds to be at least 70.656 MHz. Therefore, the data-path needs to atleast process the ADC data at that rate. Therefore, the system clockfrequency can be chosen as 70.656N MHz, where the factor N≧1 and usuallyN is chosen as an integer in practical implementation. Another importantfactor in choosing the system clock is the ASIC processing technologybecause the ASIC processing technology determines how fast the keycircuits such as multiplier can switch within one system clock cycle. Inour system we choose 141.312 MHz with N=2. However, our time-domainequalizer architecture does not really depend on a particular systemclock frequency. For 0.13 um or 0.18 um ASIC processing, it will be noproblem to run a 16×16 multiplier in a single clock cycle of 141.312MHz. Since the multiplier is a very costly hardware component, anefficient time-domain equalizer design shall always try to optimize thenumber of multipliers. On the other hand, the system performancerequirement determines the number of multiplications that thetime-domain equalizer has to carry out. Therefore, the question reallybecomes how efficiently each multiplier is used in the time-domainequalizer.

Since here we propose a general time-domain equalizer, we do not discusshow many multipliers are actually needed to support for all VDSL2profiles. We assume that a total of M multipliers are available toimplement the time-domain equalizer. The optimal design of efficientlyusing multipliers is to make sure that the full computational power ofthe multipliers is used. In other words, the multiplier shall beutilized for multiplication at every system clock cycle. This isactually the basic starting point of our time-domain architecturedesign. Given a total of M multipliers and 70.656N MHz system clockfrequency, our time-domain architecture is able to support up to thefollowing time-domain equalizer filter tap length:

Example With Profile Maximum TEQ Tap Length M = 8, N = 2 30a M × N 1612a, 12b, 17a 2 × M × N 32 8a, 8b, 8c, 8d 4 × M × N 64 ADSL2 + 16 × M ×N  256 Dowstream

The above tap length is only the upper-bound based on the multiplierprocessing capability. To minimize the hardware cost, the first step isto find the number of required multipliers to support all profiles. Nowwe assume that through the system simulation, we found that the 30aprofile requires T₀ taps, 12a, 12b, 17a profiles require T₁ taps, 8a,8b, 8c, 8d profiles require T₂ taps, ADSL2+ downstream requires T₃ taps.The problem becomes to find the optimal M value to satisfy the followingcondition:

M×N≧T ₀,2×M×N≧T ₁,4×M×N≧T ₂,16×M×N≧T ₃,

which results in

${M_{OPT} = \left\lfloor {\max \left( {\frac{T_{0}}{N},\frac{T_{1}}{2N},\frac{T_{2}}{4N},\frac{T_{3}}{16N}} \right)} \right\rfloor},$

where └.┘ means roundup to the closest integer.

After finding the optimal number of required multipliers M_(OPT), theactual number of taps can be supported for each profile becomesM_(OPT)×N, 2×M_(OPT)×N, 4×M_(OPT)×N, 16×M_(OPT)×N respectively and aredefinitely larger than each profile requirement T₀, T₁, T₂, T₃. Now thenext step is to find the mechanism so that the multipliers can beefficiently in a way that every cycle the multiplier carries out amultiplication operation. In additional the number of time-domainequalizer taps can be programmable in a flexible approach. In ourscheme, we use M_(OPT) as our base and design a mechanism so that thesupported TEQ taps are multiple of M_(OPT), i.e., M_(OPT)×l and l≦L is aprogrammable factor set by the firmware and L corresponds to the maximumsupported tap length. In order to running M_(OPT) multipliers at thesame time, we need to split the data delay-line d(k), k=0, 1, . . . ,M_(OPT)×l−1 and the coefficients c(k), k=0, 1, . . . , M_(OPT)×l−1 intol segments of M_(OPT) each. Thus the computation of FIR filter can beformulated as the following (here we only take one computation instancesince we focus on hardware implementation):

$\quad\begin{matrix}{{TEQ} = {\sum\limits_{k = 0}^{{M_{OPT} \times l} - 1}{{d(k)}{c(k)}}}} \\{= {\sum\limits_{k_{2} = 0}^{l - 1}{\sum\limits_{k_{1} = 0}^{M_{OPT} - 1}{{d\left( {{k_{2}l} + k_{1}} \right)}{c\left( {{k_{2}l} + k_{1}} \right)}}}}}\end{matrix}$

Here we only proposed one way of breaking the time-domain equalizercomputation. There are other different ways as well and we do notenumerate them one by one. The fundamental idea is to break thetime-domain equalizer computation into multiple segments to fit themultiplier computation that may run every system clock cycle.

FIG. 1 shows our time-domain equalizer hardware architecture. TheADC_DATA comes from the ADC in the analog-front-end and the ADC_DATA_RDYis used to qualify the ADC_DATA. How often the ADC_DATA is pushed intoour time-domain equalizer actually depends on the Nyquist frequency ofthe profile. For lower-speed profiles, the rate of ADC_DATA is lowerproportionally. In other words, more system clock cycles will beavailable for lower-speed profiles between two consecutive ADC_DATA_RDYassertions. This is actually the basic idea of our time-domain equalizerhardware: to explore the physical signal property to efficiently utilizecostly ASIC components such as multipliers. The ADC_DATA_RDY assertionwill advance the data delay-line as shown by the MUXs among the delayline registers. The Stage l Counter is reset by the ADC_DATA_RDYassertion and then it will start the counting process from zero until itreaches the configuration register L. The register L actually determineshow many taps the time-domain equalizer is configured (M_(OPT)×L to bemore precise). The register L is configured by the firmware through themicroprocessor interface. There is a maximum limit for the register Lbased on different profile according to how many system clock cyclesbetween two consecutive ADC_DATA_RDY. The purpose of the Stage l Counteris to control which taps and corresponding coefficients are multiplexedinto the M_(OPT) multipliers. The results of those multiplications aresummed together. In our diagram, we do not split the addition process.However, if the ASIC process speed is a concern for the adder, we cansee that the addition can split into multiple adders with some registersto hold the partial-summation results, which we do not show in thisFIGURE.

The accumulator basically accumulates and stores the summation resultsfor different stages. When the Stage l Counter is reset to zero and thefirst summation

$\sum\limits_{k = 0}^{M_{OPT}}{{d(k)}{c(k)}}$

is directly clocked into the accumulator. Otherwise, the accumulator isadded together with the summation from the current stage and stored.When the Stage l Counter reaches the final stage L, it will signal theTEQ_OUT_RDY to next module in the data-path to latch the TEQ_OUT_DATAfrom the accumulator.

In our design, the tap coefficients c(k), k=0, 1, . . . , M_(OPT)×l−1are configurable and adapted through the microprocessor interface. So,the TEQ algorithm of finding the optimal coefficients for thetime-domain equalizer runs on the microprocessor while the TEQ filtercomputation is done in hardware.

While the invention has been described with reference to exemplaryembodiments, it will be understood by those skilled in the art thatvarious changes may be made and equivalents may be substituted forelements thereof without departing from the scope of the invention. Inaddition, many modifications may be made to adapt a particular situationor material to the teachings of the invention without departing from theessential scope thereof. Therefore, it is intended that the inventionnot be limited to the particular embodiment disclosed as the best modecontemplated for carrying out this invention, but that the inventionwill include all embodiments falling within the scope of the appendedclaims.

1. A time-domain equalizer, comprising: M_(OPT) multipliers,${M_{OPT} = \left\lfloor {\max \left( {\frac{T_{0}}{N},\frac{T_{1}}{2N},\frac{T_{2}}{4N},\frac{T_{3}}{16N}} \right)} \right\rfloor},$wherein T₀ being the taps required by the 30a profile of VDSL2, T₁ beingthe taps required by the 12a, 12b, 17a profile of VDSL2, T₂ being thetaps required by the 8a, 8b, 8c, 8d profile of VDSL2, T₃ being the tapsrequired by ADSL2+ downstream; and the factor N≧1 and usually beingchosen as an integer; wherein the multiplier carrying out amultiplication operation at every system clock cycle.
 2. The equalizerof claim 1, wherein the supported TEQ taps are multiple of M_(OPT),i.e., M_(OPT)×l, l≦L and l is a programmable factor set by the firmware,and L corresponds to the maximum supported tap length.
 3. The equalizerof claim 1, wherein the time-domain equalizer computation is broke intomultiple segments to fit the multiplier computation that may run everysystem clock cycle.
 4. The equalizer of claim 3, wherein the datadelay-line d(k), k=0, 1, . . . , M_(OPT)×l−1 and the coefficients c(k),k=0, 1, . . . , M_(OPT)l−1 are split into l segments of M_(OPT) each,thus the computation of TEQ as: $\quad\begin{matrix}{{TEQ} = {\sum\limits_{k = 0}^{{M_{OPT} \times l} - 1}{{d(k)}{c(k)}}}} \\{= {\sum\limits_{k_{2} = 0}^{l - 1}{\sum\limits_{k_{1} = 0}^{M_{OPT} - 1}{{d\left( {{k_{2}l} + k_{1}} \right)}{c\left( {{k_{2}l} + k_{1}} \right)}}}}}\end{matrix}$
 5. The equalizer of claim 4, wherein the said equalizer isconfigured so that: the ADC_DATA coming from the ADC in theanalog-front-end is pushed into the time-domain equalizer depending onthe Nyquist frequency of the profile; the ADC_DATA_RDY is used toqualify the ADC_DATA and the ADC_DATA_RDY assertion will advance thedata delay-line (MUXs) among the delay line registers (d( . . . )Regs);the Stage l Counter to control which taps and corresponding coefficientsare multiplexed into the M_(OPT) multipliers, it being reset by theADC_DATA_RDY assertion and then it will start the counting process fromzero until it reaches the configuration register L; the results of thosemultiplications are summed together; the accumulator basicallyaccumulates and stores the summation results for different stages; whenthe Stage l Counter is reset to zero and the first summation$\sum\limits_{k = 0}^{M_{OPT}}{{d(k)}{c(k)}}$ is directly clockedinto the accumulator; otherwise, the accumulator is added together withthe summation from the current stage and stored; and when the Stage lCounter reaches the final stage L, it will signal the TEQ_OUT_RDY tonext module in the data-path to latch the TEQ_OUT_DATA from theaccumulator.
 6. The equalizer of claim 5, wherein the register L isconfigured by the firmware through the microprocessor interface.
 7. Theequalizer of claim 5, wherein there is a maximum limit for the registerL based on different profile according to how many system clock cyclesbetween two consecutive ADC_DATA_RDY.
 8. The equalizer of claim 5,wherein the addition can be split into multiple adders with someregisters to hold the partial-summation results if the ASIC processspeed is a concern for the adder.
 9. The equalizer of claim 5, whereinthe tap coefficients c(k), k=0, 1, . . . , M_(OPT)×l−1 are configurableand adapted through the microprocessor interface.
 10. The equalizer ofclaim 5, further comprising to utilize the time-shared multipliers tosupport different time-equalization requirement for different profilesso that it can support longer deployment loops without additionalmultipliers for finite impulse response filter.